Metastability resolved monolithic analog-to-digital converter

ABSTRACT

An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the digital latch captures the state of the Gray code counter. Metastability in the digital latch is resolved by a latch train. The Gray coded output is then decoded by a Gray decoder to a standard binary output. An array of converters are constructed on a monolithic integrated circuit where each converter shares a single analog ramp generator, binary Gray code counter and Gray decoder. A multiplexer selects a particular converter and switches the standard binary output from the selected converter to line drivers to be used off-chip. The two least significant bits of the Gray code are generated with phase shifting circuits.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to analog-to-digital convertersand more particularly to multiple analog-to-digital convertersintegrated on a monolithic integrated circuit.

2. Discussion of the Related Art

In conventional single slope methods of analog-to-digital conversion, aclocked comparator is employed to compare a sampled and held signal withan analog ramp. The clocked comparator in turn generates a signal thatis used to clock a latch circuit that stores the state of a digitalcounter when the sampled and held signal is equal to the analog ramp.The stored counter value is a digital representation of the magnitude ofthe analog signal. Integrated circuit applications of this type ofcircuit provide an array of such circuits.

Conventional single slope analog-to-digital converters encounterresolution and speed limitations due to limitations on maximum clockrate. One limit to the maximum clock rate with the convention singleslope converter is due to metastability. Metastability is defined as theinstability of a flip-flop when the clock and data inputs changesimultaneously. Although the output of a flip-flop cannot, in principle,be guaranteed to have settled to a valid logic state after any givenperiod of time, the probability that the output has not settleddecreases exponentially with time. After about 69 time constants, forexample, the probability of the output not settling is less than 10⁻³⁰,which is acceptable for most applications.

Due to this problem, the clock rate must be reduced substantially toallow the flip-flop, which synchronizes the comparator output to thesystem clock time, to recover from metastability. Conventional devicesrequire the metastability resolution to be done at a frequencydetermined by the time resolution of the conversion. As a result,conventional devices are limited to clock rates much less than theircircuits are capable of.

The invention improves on conventional devices by removing therequirement to synchronize individual converters to the master clock andby generating a higher resolution digital code. It is therefore oneobject of the invention to provide an analog-to-digital converter thatrealizes a significant improvement in resolution and speed compared toconventional converters.

SUMMARY OF THE INVENTION

The invention provides an apparatus to convert an analog signal to adigital signal comprising: an analog ramp generator having an analogramp output, a digital ramp generator having a Gray coded digital rampoutput, a comparator for comparing the analog signal with the analogramp signal, wherein the comparator has a comparison output, and ametastability resolving latch for storing data having a first data inputconnected to the digital ramp output and an enable input connected tothe comparison output, wherein the metastability resolving latch has ametastability resolved digital signal output.

The invention also provides an apparatus to convert a plurality ofanalog signals to a plurality of digital signals comprising: an analogramp generator having an analog ramp output, a digital ramp generatorhaving a Gray coded digital ramp output, a plurality of comparators forcomparing the analog signal with the plurality of analog ramp signals,wherein the plurality of comparators has a plurality of comparisonoutputs, and a plurality of metastability resolving latches for storingdata having a plurality of first data inputs connected to the digitalramp output and a plurality of enable inputs connected to the comparisonoutput, wherein the plurality of metastability resolving latches have aplurality of metastability resolved digital signal outputs.

The invention also provides an analog-to-digital conversion methodcomprising the steps of operating an unclocked comparator to compare aninput analog voltage to a voltage ramp to enable a digital latch tostore a Gray coded digital timer word when the two comparator inputs aresubstantially equal.

The features and advantages of the present invention will be morereadily understood and the apparent from the following detaileddescription of the invention, which should be read in conjunction withthe accompanying figures, and from the claims which are appended at theend of the detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are incorporated herein by reference and in whichlike elements have been given like reference characters,

FIG. 1 is a schematic block diagram of an analog-to-digital converteraccording to the invention;

FIG. 2 is a schematic block diagram of the metastability resolvingcircuit illustrated in FIG. 1;

FIG. 2A is a schematic block diagram of the analog waveform generatorillustrated in FIG. 1;

FIG. 3 is a schematic block diagram of an array of analog-to-digitalconverters according to the invention;

FIG. 4 is a schematic block diagram of the clock multiplying phaselocked loop illustrated in FIG. 3;

FIG. 5 is a schematic block diagram of the 90° phase shifter illustratedin FIG. 3;

FIG. 6 is a schematic block diagram of an alternate embodiment of thecircuit illustrated in FIG. 3;

FIG. 7 is a schematic block diagram of a two phase voltage controlledoscillator and squaring circuit used in the circuit of FIG. 6;

FIG. 8 is a detailed schematic circuit diagram of the voltage controlledoscillator illustrated in FIG. 7;

FIG. 9 is a detailed schematic circuit diagram of the squaring circuitillustrated in FIG. 7; and

FIG. 10 is a timing diagram illustrating the temporal relationship amongthe least significant bits of the Gray code signal.

DETAILED DESCRIPTION

For purposes of illustration only, and not to limit generality, thepresent invention will now be explained with reference to particularembodiments and operational parameters. One skilled in the art willappreciate, however, that the present invention is not limited to theparticular operational parameters described.

Reference is now made to FIG. 1, which is an overall schematic blockdiagram of the analog-to-digital converter of the invention. Analoginput signal 15, the analog signal to be converted, is connected to oneinput of an unclocked analog comparator 20. The other input of thecomparator 20 is connected to an analog ramp signal 18. Analog waveformgenerator 30 generates the analog ramp signal 18. When the analog rampsignal 18 substantially equals the analog input signal 15, thecomparator generates output signal 21. The comparator output signal 21is connected to a control input of a metastability resolving circuit 35.Synchronized with the analog waveform generator 30 is a Gray codegenerator 45 that generates a digital Gray code on a digital Gray codebus 62. The digital Gray code bus 62 is connected to a data input of themetastability resolving circuit 35. The metastability resolving circuit35 stores the states of the digital Gray code on bus 62 in response toan active state of the comparator output signal 21. As a result, thedigital output signal 47 of the metastability resolving circuit 35 is adigital representation of the magnitude of the analog input signal 15when the magnitude of the analog ramp signal 18 equals the magnitude ofthe analog input signal 15.

Reference is now made to FIG. 2, which illustrates the metastabilityresolving circuit 35 in more detail. Comparator output signal 21 isconnected to the control input of an N-Bit data latch 11. N is thenumber of bits of resolution that the analog signal 15 is digitized(converted) into by the analog-to-digital converter. N can be any numberand is typically between eight and sixteen for most applications. TheN-bit data latch 11 data input is connected to the digital Gray code bus62 from the Gray code generator 45. The data latched by the N-bit datalatch 11 (which is a code generated by Gray code generator 45) isprovided on line 17 to N-bit flip-flop 19. N-bit flip-flop 19 resolvesthe metastability of the system by storing the data on line 17 apredetermined time period after the N-bit data latch 11 has stored thestate of the Gray code generator 45. The digital output 47 is providedas described above.

Reference is now made to FIG. 2A, which illustrates a schematic blockdiagram of analog waveform generator 30 illustrated in FIG. 1.Operational amplifier 32 provides the analog ramp signal 18 by providingan output signal to integration capacitor 28. RESET signal 34 isgenerated by timing circuit 33 and activates switch 28A to dischargecapacitor 28 when a new conversion is to be initiated. One input 39 ofoperational amplifier 32 in connected to a RAMP_BIAS signal and a secondinput 23 is connected to the output of a programmable current source 31.Programmable current source 31 is controlled by operationaltransconductance amplifier 27. Amplifier 27 has a first input connectedto the analog ramp signal 18. A second input of amplifier 27 isconnected to a ramp reference voltage RAMP_REF. A third input ofamplifier 27 is connected to the output of ramp adjust circuit 29. Thestarting voltage of the analog ramp is adjustable by changing theRAMP_BIAS voltage. The slope of the analog ramp signal 18 is controlledby amplifier 27. By changing the output of programmable current source31 in response to a current signal 27A from transconductance amplifier27, the slope of the analog ramp signal 18 can be changed. In responseto control signal 33A from timing circuit 33, issued just before rampsignal 18 is to terminate, ramp adjust circuit 29, via control signal29A, turns amplifier 27 on to sample the difference between the RAMP_REFvoltage and the voltage of analog ramp signal 18. Transconductanceamplifier 27 converts this voltage difference to a current 27A that isused to control programmable current source 31. After programmablecurrent source 31 has been adjusted, timing circuit 33, via controlsignal 33A, turns amplifier 27 off to open the feedback loop, issuesRESET signal 34 to discharge capacitor 28 using switch 28A, and thenopens switch 28A to begin another integration cycle.

Reference is now made to FIG. 3, which is a schematic block diagram ofparallel analog-to-digital converters 10A and 10B. Only two convertersare shown for clarity; there could be m number of converters in anarray. In one preferred embodiment there are 328 converters in an array.Each analog-to-digital converter is connected to the digital Gray codebus 62 and an output bus 57. The digital Gray code bus 62 is connectedto each data input of the m data latches. For clarity, only theconnections to data/latches 24A and 24B are shown. The data input ofeach data latch is driven by the gray code generator 45. The N-bitoutput bus 57 is connected to the data output of each transfer latch(latches 26A and 26B being illustrated) and is read by multiplexerreadout circuit 59.

The analog signal on line 15A, the signal to be converted, is stored bycapacitor 23A until sampling switch 12A is closed, thereby transferringthe charge to capacitor 16A. Capacitor 16A integrates the analog signal15A until switch 12A is opened. After a predetermined time interval haspassed, switch 12A is opened and switch 25A is closed, thus resettingcapacitor 23A at the start of each conversion period. Those skilled inthe art will recognize that any charge transfer device or circuit may beused to transfer the signal to be compared. During the read out phasethe sampled signal 14A is compared to an analog ramp signal 18 bycomparator 20A. When the sampled signal 14A is equal to or at somepredetermined potential with respect to the analog ramp signal 18, theoutput 22A of the comparator 20A activates latch 24A. The output of thecomparator 20A is connected to the enable input of latch 24A. The latch24A, connected to digital Gray code bus 62, stores the state of the graycode count at the time the analog ramp signal 18 equals the sampledsignal 14A in response to comparator output signal 22A. The output oflatch 24A is provided to a transfer latch 26A. Output control shiftregister 54, connected to transfer latches 26A and 26B via outputs 70Aand 70B, selects the output of a particular analog-to-digital converterfrom the array of converters. The output of each transfer latch isconnected to sense amplifier 53 via N-bit output bus 57, part ofmultiplexer readout circuit 59. Only one transfer latch is active andsupplying an output to bus 57 at any one time. The output controlregister 54 is synchronized with input clock 68.

Multiplexer readout circuit 59 will now be described. One skilled in theart will appreciate that each of the circuit blocks in multiplexerreadout circuit 59 is N-bits wide to accommodate the number of bits fromeach transfer latch. The output of sense amplifier 53 is connected tothe input of input resister 55 which is clocked by input clock 68. Inputregister 55 latches the data on N-bit output bus 57 from whichever N-bittransfer latch has been enabled by output control shift register 54. Theoutput of register 55 is connected to the input of a metastabilityresolving register 36 that is also clocked by input clock 68.Metastability resolving register 36 is clocked so that one full clockcycle after the state of N-bit output bus 57 has been latched into inputregister 55, the data from input register 55 is provided to the input ofmetastability resolving register 36. Register 36 resolves themetastability of the conversion that may have arisen when the digitalsignal on bus 62 was latched by output signal 22A from analog comparator20A. Circuit analysis of this latch train arrangement has indicated thatthe metastability of the system is improved by a factor of at least 2³⁰by the addition of metastability resolving register 36. The output ofthe metastability resolving register 36 is connected to a Gray codedecoder 38 that converts the Gray code signal to a standard binarysignal. The Gray code decoder 38 may use an exclusive-ORing (XORing)process in which the output of each latch in the metastability resolvingregister 36 is exclusive-ORed (XORed) with an adjacent bit that has inturn been exclusive-ORed with another bit, and so on. The standardbinary N-bit code output by Gray code decoder 38 is provided to the datainput of N-bit output register 71, which latches the output value inresponse to input clock 68. The output of output register 71 is providedto N output drivers 73 that provide the N-bit converted binary outputsignal 47.

Input clock 68 is also provided to a clock multiplying phase locked loopcircuit 50 that generates a high speed clock 64. In one embodiment ofthe invention, the clock multiplier is a 12× clock multiplier. In oneembodiment of the invention, for example, input clock 68 is a 7MHznominal clock and clock multiplier 50 increases this by a factor of 12to 84 MHz.

Gray code generator 45 will now be described. The digital Gray code onbus 62, which in one embodiment of the invention is an N-bit binary graycode, is generated by concatenation of three bit streams: a leastsignificant bit 60, a next-to-least significant bit 58 and a N-2 bitgray code word 56. The high speed clock 64 clocks an N-2 bit synchronousbinary counter 48. The N-2 bit synchronous counter 48 provides an outputsignal to an N-2 bit Gray code encoder 46. The Gray code encoderprovides the N-2 most significant bits 56 of the digital Gray code onbus 62 via output synchronizing register 51 and line drivers 61. Graycode encoder 46 provides a Gray code by XORing each bit output bycounter 48 with an adjacent output bit.

The high speed clock 64 and the N-2 bit synchronous counter's leastsignificant bit 49 is connected to a negative edge triggered flip-flop44. The negative edge triggered flip-flop 44 provides the next to leastsignificant bit signal, LSB+1 58, as part of the digital Gray code onbus 62.

The high speed clock 64 is also connected to a 90° analog phase shifter42. The 90° phase shifter 42 generates the least significant bit signal,LSB 60, as part of the digital Gray code on bus 62 by shifting the highspeed clock 64 by 90°.

In one example embodiment, N is equal to 13 bits, synchronous counter 48and Gray code encoder 46 provide the 11 most significant bits on Graycode bus 62. A 12th bit (LSB+1) is supplied by dividing a 75(approximately) MHz clock by two and then latching it with the fallingedge of the 75 MHz clock in flip-flop 44. The 13th bit (LSB) isgenerated by delaying the 75 MHz clock by precisely 90°, ¼ of a completeclock cycle, in closed loop phase shifter 42. This type of phase shifteris sometimes referred to as a delay locked loop.

Reference is now made to FIG. 4, which illustrates in more detail, theclock multiplying phase locked loop 50 of FIG. 3. Clock multiplier 50includes a phase detector 100 that detects a difference in phase betweeninput clock 68 and a frequency divided version of high speed clock 64 online 102. The output 104 of phase detector 100 is used to control afrequency multiplying voltage controlled oscillator (VCO) 106. VCO 106increases the frequency of input clock 68 by a predetermined factor. Inone example, VCO 106 increases the frequency of input clock 68 by afactor of 12 to produce high speed clock 64. The output 108 of VCO 106is provided to a “squaring” circuit 110. The function of squaringcircuit 110 is to shape the output signal 112 so that high speed clock64 has a fit percent duty cycle, i.e., a “square” output. High speedclock 64 is also provided to a divide by n circuit 114 that divides thefrequency by a factor n so that the frequency of the clock signaldelivered on line 102 is equal to the frequency of input clock 68. Asdiscussed before, in one embodiment, if VCO 106 increases the clockfrequency by a factor of 12, then n would be 12 so that divide by ncircuit 114 reduces the frequency of high speed clock 64 by a factor of12 before providing that signal to phase detector 100. In oneembodiment, VCO 106 may include a ring oscillator.

Reference is now made to FIG. 5, which FIG. is a schematic block diagramof the 90° analog phase shifter 42 illustrated in FIG. 3. High speedclock 64 and its complement from clock multiplier 50 are connected tothe first and second clocking inputs of a four input exclusive or (XOR)gate 80. XOR gate 80 includes an output coupled to the inverting inputof a high gain integrating amplifier 82. Amplifier 82 outputs a controlsignal 83 which is coupled to a control input of a voltage controlleddelay circuit 78. The voltage controlled delay circuit 78 also receivesa clocking signal from the high speed clock 64. The high gain ofamplifier 82 ensures that the delay is always 90° even in the presenceof variations in component values and clock frequency. The voltagecontrolled delay circuit 78 outputs a delayed signal in response to thecontrol signal 83 and clock 64 to a “squaring” circuit 77. Squaringcircuit 77 shapes the delayed signal so that it is symmetrical and has afifty percent duty cycle (i.e., a “square” output) and outputs a signalto the input of line driver inverter 75. Squaring circuit 77 is similarto squaring circuit 110, previously described. Line driver inverter 75outputs a first line driver inverter signal 75A and a second line driverinverter signal 75B to third and fourth inputs of the four inputexclusive OR gate 80. The first and second line driver inverter signalsare also coupled to first and second inputs of a delay matching circuit81. Signals 75A and 75B comprise a complementary delayed clock. Delaymatching circuit 81 ensures that the delay experienced by each signal75A and 75B is the same, so that the signals remain in the proper phaserelationship with each other. The delay matching circuit 81 outputs LSB60.

Reference is now made to FIG. 6, which is a schematic block diagram ofan alternate embodiment of the circuit of FIG. 3. In the circuit of FIG.6, the 90° phase shifter 42 of FIG. 3 has been eliminated. In addition,clock multiplier 50 has been modified so as to provide LSB 60 directly.In all other respects, the operation of FIG. 6 is the same as alreadydescribed in connection with FIG. 3.

Reference is now made to FIG. 7, which FIG. is a schematic block diagramof the clock multiplier 50 of FIG. 6. In FIG. 7, as in FIG. 4, inputclock 68 is provided to a phase detector 100 that provides a controlsignal 104, in response to input clock 68 and signal 102, to a voltagecontrolled oscillator 120. VCO 120 also multiplies the output frequencyprovided on line 108 to squaring circuit 110 in order to generate highspeed clock 64 on line 112. The output of squaring circuit 110 on line112 is additionally provided to divide by n circuit 114 that deliverscontrol signal 102 in the same manner as described in connection withFIG. 4.

VCO 120 also provides a second output 122 that is phase shifted 90° withrespect to output 108 and then provided to another squaring circuit 110.Squaring circuit 110 operates in the manner described in connection withFIG. 4 to provide a “square” output for the LSB 60 on line 124.

Reference is now made to FIG. 8, which FIG. is a schematic diagram ofVCO 120. VCO provides two outputs 108, 122 that are 90° out of phasefrom each other. VCO 120 is a ring oscillator formed from an odd numberof invertor stages connected in a loop. In particular, VCO 120 includesinverters 126, 128, 130, 132, and 134. The output of inverter 134 isconnected via line 136 to the input of inverter 126 in order to form thering. If t is the time delay of one of the inverters and p is the numberof stages in the oscillator, then the oscillation frequency f is:

f=1/(2pt)  (1)

Changing the frequency is accomplished by changing the power supplyvoltage of the invertor chain, thus changing time t. In the case of theCMOS invertor, the propagation delay increases as the supply voltage isdecreased.

The phase shift per stage in the ring oscillator is:

Phase/stage=180/p  (2)

For example, in the five stage oscillator illustrated in FIG. 8, thephase shift per stage is 36°. Thus, a tap two stages away from the mainoutput will have a 72° phase shift, while a tap three stages away fromthe main output will have a 108° phase shift. If all of the invertersare identical, then a 90° phase shift is not possible.

However, if the different investors in the ring oscillator are notidentically constructed, then a 90° phase shift between invertors in thering oscillator can be obtained. In a CMOS inverter, the delay throughthe inverter depends upon a number of factors, including the size andshape of the component transistors and the amount of capacitive loadingon its output. Adjusting any of these factors to increase thepropagation delay of one of the inverters with respect to the remaininginverters in the ring can be used to provide the required 90° phaseshift.

In VCO 120 illustrated in FIG. 8, the propagation delay of inverter 130is adjusted by adding two transistors 138 and 140 that are biased so asto always be in the on state. This increases the propagation delaythrough inverter 130 so that the total delay through inverters 134, 126,and 128 is about the same as the delay through modified inverter 130 andinverter 132. If the delay through inverters 134, 126, and 128 is thesame as the delay through modified inverter 130 and inverter 132, thenthere is exactly a 90° phase shift between outputs 108 and 122.

Reference is now made to FIG. 9, which FIG. is a schematic circuitdiagram of squaring circuit 110 illustrated in FIGS. 4 and 7. Squaringcircuit 77 is FIG. 5 also operates in the same manner as squaringcircuit 110.

As illustrated in FIG. 9, the output of VCO 120 is provided to squaringcircuit 110. Obviously, in the case of the circuit illustrated in FIG.7, two squaring circuits are provided, one for each output of VCO 120.

Typically, VCO 120 operates at a reduced voltage compared to the rest ofthe circuitry and therefore outputs 108 and 122 need to be translated tothe higher voltage level of the rest of the circuits. In addition, thepropagation delay generally will not be the same for the rising andfalling edges of the output signal and therefore the output of the leveltranslator circuit will not be symmetrical, i.e., have a “square” outputor fifty percent duty cycle, even though the signals internal to thering oscillator are symmetric. Circuit 110 thus incorporates the leveltranslator into a closed loop feedback circuit that adjusts the inputthreshold as needed to maintain the symmetry of the output signal.

The level shifter includes transistors 150 and 152, and inverters 154and 156. Two current source transistors 158 and 160 are controlled byvoltages VMINUS and VPLUS. The voltages VMINUS and VPLUS are supplied bycurrent mirror 162 and control the amount of current delivered by thetransistors 158 and 160. A feedback loop of signal 112 or 124 isprovided through transistors 158. 160, transistor 164, to level shiftingtransistors 150 and 152. If the waveform of output signal 112 or 124becomes asymmetrical, i.e., not “square”, transistors 158, 160 respondby changing the gate voltage on the input stage current sourcetransistor 150 in a direction that reestablishes symmetry of the output.Additionally, transistor 164, used as a capacitor, filters out anyripple voltage and sets the response time of the feedback loop.

Reference is now made to FIG. 10, which is a timing diagram of the LSB60 and LSB+1 58. The timing diagram of FIG. 10 illustrates the operationof either the circuit of FIG. 3 or the circuit of FIG. 6. The high speedclock 64 transitions from low to high at time 3. The least significantbit 49 of the N-2 bit binary counter 48 transitions on the low to hightransition of the high speed clock 64. The LSB 60, derived from the highspeed clock 64, transitions high at time and low at time 9. The LSB+158, derived from the counter least significant bit 49, transitions highat time 7 and low at time 2. The N-2 most significant bits 56 of theGray encoded signal transition only at time 3 while the LSB 60 and LSB+158 signals do not change at time 3. At times 2, 5, 7, and 9 only one ofthese signals changes at a time, thus meeting the Gray code requirementof having only a single bit change when there is a change in the count.

One skilled in the art will appreciate that rather than using an inputclock having a frequency that is multiplied in order to provide a highspeed clock, an external high speed clock could be used to controlcounter 48, flip-flop 44, and 90° phase shifter 42.

One advantage of the present invention is that the Gray code leastsignificant bit frequency may be equal to the frequency of the clockthat is used to control the circuit. This means that the leastsignificant bit frequency may be equal to the maximum toggle frequencyfor the flip-flop. Conventionally, for a typical Gray code, the masterclock frequency is four times the frequency of the least significant bitof the Gray code. In the present invention, by contrast, the frequencyof the least significant bit of the Gray code can be equal to the clockfrequency. Therefore, the clock frequency is only limited by theinherent frequency limitations of the clock counter circuitry itself.This allows for higher conversion rates then conventionally achievable.

For a typical 2 micron CMOS process at room temperature, this frequencylimit is about 150 MHz, and about 500 MHz at 80° K. For a typical 1micron CMOS process, this frequency limit is about 500 MHz at roomtemperature, and may be more than 1 Ghz at 80° K. In one embodiment ofthe invention, a 72 MH master clock generates a Gray code with 3.5 nsresolution which allows a 13 bit conversion in 30 μs. A 500 MHz masterclock generates a Gray code with 500 ps resolution, allowing a 16 bitconversion in 33 μs or 12 bits in 2 μs. With several hundred of theseconverters on one chip, the total conversion rate may be on the order of100 MHz. The estimated power is less than 50 μw per channel. As aresult, the present invention allows the relatively slow single slopemethod of analog-to-digital conversion, when a array of such convertersare used on a single chip, to provide relatively high conversion rates,while consuming low amounts of power. Furthermore, the simple design ofsingle slope analog-to-digital converters saves power and allowsintegration of a large number of these converters on a single integratedcircuit, particularly when using CMOS technology.

A Gray code count is used as the digital signal to be stored when thecomparator is activated because, by definition, only one bit changes foreach increment of the code. Since only one of the Gray coded bits can bein the process of changing when the latch is enabled, only one of thesampled bits can exhibit metastability, and the resultant code will beuncertain by only one least significant bit. This is in contrast to thecase when a standard binary code is used as the digital signal to bestored. Since more than one bit may be changing for each increment ofthe code, a number of the sampled bits can exhibit metastability.

The use of a Gray code count also advantageously allows themetastability resolution to be determined at a point in the circuitwhere there is more time to complete it, thus reducing the power andspeed requirements of the circuitry. As a result, in the presentinvention, the metastability resolution can be postponed until after themultiplexing of the data when the data rate is considerably lower thanthe rate at which the data is provided by each analog-to-digitalconverter. In particular, in conventional circuits, the metastabilityresolution might typically be provided when the binary code from acounter is clocked into the N-bit data latches. This might require themetastability resolution to be performed in a very short time intervalat a relatively high clock rate. As noted, by contrast, the presentinvention can accomplish this function using a significantly lower clockrate, which reduces the power and speed requirements of the circuitry.

For example, a 75 MHz (approximately) clock may be used to generate theGray code. This 75 MHz clock is generated from a 6 MHz (approximately)input clock. The 75 MHz clock is used only for the analog-to-digitalconversion; the 6 MHz clock is used for all other functions of theintegrated circuit.

By using an array of 328 converters, a conversion is completed inapproximately 30 microseconds with a resolution of 13 bits. Aconventional approach requires a master clock frequency of approximately300 MHz, which is higher than the capability of, for example, aconventional 2 micron CMOS process. The use of a gray code allows themetastability resolution to be performed at a rate of 6 MHz on 13 bitsrather than 300 MHz on 328 comparators.

The invention also provides a method of converting the analog signalsfrom an array of analog-to-digital converters with a high effectiveclock rate, and increased resolution. A multitude of input signals, onefor each converter, are sampled and held. Signals are formed byintegrated the current from an analog source. This signal is heldconstant on a capacitor for the duration of the conversion process.Next, an analog ramp and a digital counter are simultaneously started. Acomparator circuit compares the voltage of the ramp with the sampled andheld voltage. When the two are equal, the output of the comparatorchanges state and causes the value of the digital counter to be storedin an N bit latch. The values stored in the array of latches, which area digital representation of the various input voltages, are transferredin parallel to another array of latches. Then a new set of conversionscan be performed while the results of the previous conversions aremultiplexed to form a digital output signal.

For an array of converters, the digital counter and ramp generator arecommon to all converters. Each converter itself needs only a sample andhold, a comparator, and an array of digital latches.

The circuits of the present invention may be monolithically integratedin semiconductor form using convention CMOS technology.

Having thus described at least one illustrative embodiment of theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be within the spirit andscope of the invention. Accordingly, the foregoing description is by wayof example only and is not intended as limiting. The invention islimited only as defined in the following claims and the equivalentsthereto.

What is claimed is:
 1. Apparatus comprising: at least one convertercircuit to convert an analog signal to a digital signal, the at leastone converter circuit including: counter circuit to generate a sequenceof multi-bit digital counts; and a first register, coupled to thecounter circuit, to store at least one multi-bit digital count of thesequence as the digital signal during a conversion period; and ametastability resolving circuit, coupled to the at least one convertercircuit so as to receive the digital signal, to store the digital signalat a predetermined time after the conversion period and output ametastability resolved digital signal based on the digital signal. 2.The apparatus of claim 1, wherein the at least one converter circuitfurther includes: an analog ramp generator to output an analog rampsignal; and a comparator, coupled to the analog ramp generator and thefirst register, to compare the analog signal to the analog ramp signaland to output a comparator output signal to the first register, whereinthe first register stores at least one multi-bit digital count output bythe counter circuit as the digital signal based on the comparator outputsignal.
 3. The apparatus of claim 2, wherein: the counter circuit is aGray-code counter circuit; and the at least one multi-bit digital countis at least one multi-bit Gray-code digital count.
 4. Apparatuscomprising: at least one converter circuit to convert an analog signalto a digital signal, the at least one converter circuit including afirst register to store the digital signal during a conversion period;and a metastability resolving circuit, coupled to the at least oneconverter circuit so as to receive the digital signal, to store thedigital signal at a predetermined time after the conversion period andoutput a metastability resolved digital signal based on the digitalsignal, wherein: the at least one converter circuit converts a sequenceof analog signals to a corresponding sequence of digital signals duringa sequence of conversion periods; the metastability resolving circuitincludes an input clock to store the sequence of digital signals at afirst data rate; and the at least one converter circuit includes acounter circuit input to receive a sequence of digital counts at asecond data rate, the second data rate being higher than the first datarate, each digital signal of the sequence of digital signals beingstored in the first register as one digital count of the sequence ofdigital counts.
 5. The apparatus of claim 4, wherein the metastabilityresolving circuit stores each digital signal of the sequence of digitalsignals at the predetermined time after each conversion period of thesequence of conversion periods.
 6. Apparatus comprising: at least oneconverter circuit to convert an analog signal to a digital signal, theat least one converter circuit including a first register to store thedigital signal during a conversion period; and a metastability resolvingcircuit, coupled to the at least one converter circuit so as to receivethe digital signal, to store the digital signal at a predetermined timeafter the conversion period and output a metastability resolved digitalsignal based on the digital signal, wherein: the at least one convertercircuit includes a plurality of converter circuits; the metastabilityresolving circuit further includes a multiplexer, coupled to the firstregister of each converter circuit of the plurality of convertercircuits, to select the digital signal from one of the plurality ofconverter circuits and output the selected digital signal; and themetastability resolving circuit stores the selected digital signal atthe predetermined time and outputs the metastability resolved digitalsignal based on the selected digital signal.
 7. The apparatus of claim6, further including an input clock having a first frequency, themultiplexer being coupled to the input clock so as to select a sequenceof digital signals from the plurality of converter circuits and outputthe sequence of selected digital signals at a first data rate based onthe first frequency of the input clock.
 8. The apparatus of claim 7,wherein the multiplexer outputs each selected digital signal during arespective first cycle of the input clock.
 9. The apparatus of claim 8,wherein the metastability resolving circuit further includes an inputregister, coupled to the input clock and the multiplexer, to receive thesequence of selected digital signals at the first data rate and storeeach selected digital signal during the respective first cycle of theinput clock.
 10. Apparatus comprising: at least one converter circuit toconvert an analog signal to a digital signal, the at least one convertercircuit including a first register to store the digital signal during aconversion period; and a metastability resolving circuit, coupled to theat least one converter circuit so as to receive the digital signal, tostore the digital signal at a predetermined time after the conversionperiod and output a metastability resolved digital signal based on thedigital signal, wherein: the at least one converter circuit includes aplurality of converter circuits; the metastability resolving circuitincludes a multiplexer, coupled to the first register of each convertercircuit of the plurality of converter circuits, to select the digitalsignal from one of the plurality of converter circuits and output theselected digital signal; and the metastability resolving circuit storesthe selected digital signal at the predetermined time and outputs themetastability resolved digital signal based on the selected digitalsignal, the apparatus further including an input clock having a firstfrequency, the multiplexer being coupled to the input clock so as toselect a sequence of digital signals from the plurality of convertercircuits and output the sequence of selected digital signals at a firstdata rate based on the first frequency of the input clock, wherein: themultiplexer outputs each selected digital signal during a respectivefirst cycle of the input clock; the metastability resolving circuitfurther includes an input register, coupled to the input clock and themultiplexer, to receive the sequence of selected digital signals at thefirst data rate and store each selected digital signal during therespective first cycle of the input clock; and the metastabilityresolving circuit further includes a metastability resolving register,coupled to the input clock and the input register, to receive thesequence of selected digital signals at the first data rate and storeeach selected digital signal during a respective second cycle of theinput clock after the respective first cycle, the metastabilityresolving register outputting the metastability resolved digital signalfor each selected digital signal.
 11. The apparatus of claim 10,wherein: each converter circuit includes a counter circuit input toreceive a sequence of digital counts at a second data rate, the seconddata rate being higher than the first data rate; and for each converter,the digital signal is stored in the first register as one digital countof the sequence of digital counts.
 12. The apparatus of claim 11,further including a Gray code generator to generate the sequence ofdigital counts, the Gray code generator coupled to the counter circuitinput to provide the digital signal as a Gray coded digital signal. 13.The apparatus of claim 12, wherein the metastability resolving circuitfurther includes a Gray code-to-binary converter, coupled to themetastability resolving register so as to receive the metastabilityresolved digital signal, to output a metastability resolved standardbinary digital signal based on the metastability resolved digitalsignal.
 14. The apparatus of claim 12, further including a high speedclock having a second frequency higher than the first frequency of theinput clock, wherein: the digital signal includes N bits; each digitalcount of the sequence of digital counts includes a least significantbit, a next-to-least significant bit, and (N-2) most significant bits;the Gray code generator is coupled to the high speed clock andconstructed and arranged to toggle the least significant bit at thesecond frequency of the high speed clock, such that the Gray codegenerator generates the sequence of digital counts at the second datarate.
 15. The apparatus of claim 14, wherein the second frequency of thehigh speed clock is at least 12 times higher than the first frequency ofthe input clock.
 16. The apparatus of claim 14, wherein the Gray codegenerator includes: a synchronous counter, coupled to the high speedclock, having a synchronous counter output including a counter leastsignificant bit; an XOR Gray encoder, coupled to the synchronous counteroutput, to output the (N−2) most significant bits; and a first phaseshifter, coupled to the high speed clock and the synchronous counter soas to receive the counter least significant bit, to output thenext-to-least significant bit.
 17. The apparatus of claim 16, whereinthe Gray code generator further includes a second phase shifter, coupledto the high speed clock, to output the least significant bit as a phaseshifted version of the high speed clock.
 18. The apparatus of claim 17,wherein the second phase shifter outputs the least significant bit as a90° phase shifted version of the high speed clock, the second phaseshifter including: a voltage controlled delay, having a control inputand coupled to the high speed clock, to output a delayed clock signalbased on both of the high speed clock and a control signal received atthe control input; a squaring circuit, coupled to the voltage controlleddelay so as to receive the delayed clock signal, to output a 50% dutycycle delayed clock signal; a phase detector circuit, coupled to thehigh speed clock and the squaring circuit so as to receive the 50% dutycycle delayed clock signal, to output the least significant bit and aphase signal based on a difference between the high speed clock and the50% duty cycle delayed clock signal; and an amplifier, coupled to thephase detector circuit so as to receive the phase signal, to output thecontrol signal to the voltage controlled delay.
 19. The apparatus ofclaim 16, further comprising a high speed clock generator to receive theinput clock and multiply the first frequency of the input clock tooutput the high speed clock.
 20. The apparatus of claim 19, wherein: thehigh speed clock generator includes a divider to output the high speedclock and a modified high speed clock having a third frequency less thanthe second frequency of the high speed clock; the high speed clockprovides the least significant bit; and the modified high speed clock,instead of the high speed clock, is coupled to the synchronous counterand the first phase shifter.
 21. The apparatus of claim 19, wherein theapparatus is a monolithic device integrated on a semiconductor chip. 22.The apparatus of claim 21, wherein the monolithic device is a CMOSdevice.
 23. An analog-to-digital signal conversion method, comprisingsteps of: generating a sequence of multi-bit digital counts; convertingat least one analog signal to at least one digital signal, wherein theat least one digital signal includes at least one multi-bit digitalcount of the sequence of multi-bit digital counts; storing the at leastone digital signal in a first register during a conversion period; andtransferring, at a predetermined time after the conversion period, theat least one digital signal stored in the first register to a secondregister to resolve a metastability of the at least one digital signal.24. The method of claim 23, wherein the step of converting at least oneanalog signal to at least one digital signal includes steps of:generating an analog ramp signal; and comparing the at least one analogsignal to the analog ramp signal to generate at least one comparisonsignal.
 25. The method of claim 24, wherein the step of storing the atleast one digital signal in a first register during a conversion periodincludes a step of storing the at least on digital signal in the firstregister based on the at least one comparison signal.
 26. The method ofclaim 25, wherein the step of generating a sequence of multi-bit digitalcounts includes a step of generating a sequence of multi-bit Gray codedigital counts.
 27. An analog-to-digital signal conversion method,comprising steps of: converting at least one analog signal to at leastone digital signal; storing the at least one digital signal in a firstregister during a conversion period; and transferring, at apredetermined time after the conversion period, the at least one digitalsignal stored in the first register to a second register to resolve ametastability of the at least one digital signal, wherein: the step ofstoring the at least one digital signal includes a step of storing asequence of digital signals during a sequence of conversion periodsbased on a corresponding sequence of analog signals; and the step oftransferring includes a step of transferring the sequence of digitalsignals to the second register at a first data rate.
 28. The method ofclaim 27, wherein: the step of storing a sequence of digital signalsincludes a step of storing each digital signal of the sequence ofdigital signals in the at least one corresponding first register duringeach conversion period of the sequence of conversion periods; and thestep of transferring the sequence of digital signals includes a step oftransferring each digital signal of the sequence of digital signals tothe second register at the predetermined time after each conversionperiod.
 29. The method of claim 27, wherein the step of storing asequence of digital signals includes steps of: generating a sequence ofdigital counts at a second data rate, the second data rate being higherthan the first data rate; and storing each digital signal of thesequence of digital signals in the first register as one digital countof the sequence of digital counts.
 30. An analog-to-digital signalconversion method, comprising steps of: converting at least one analogsignal to at least one digital signal; storing the at least one digitalsignal in a first register during a conversion period; and transferring,at a predetermined time after the conversion period, the at least onedigital signal stored in the first register to a second register toresolve a metastability of the at least one digital signal, wherein: thestep of converting includes a step of comparing a plurality of analogsignals to an analog ramp signal to generate a corresponding pluralityof comparison signals; and the step of storing includes a step ofrespectively storing a plurality of digital signals in a plurality offirst registers during the conversion period, each digital signal of theplurality of digital signals based on a respective analog signal of theplurality of analog signals, each digital signal being stored in arespective first register based on one comparison signal of theplurality of comparison signals.
 31. The method of claim 30, furtherincluding a step of selecting one digital signal from the plurality offirst registers before the step of transferring, wherein the step oftransferring includes a step of: transferring the one selected digitalsignal to the second register at the predetermined time after theconversion period to resolve a metastability of the one selected digitalsignal.
 32. The method of claim 31, wherein: the step of selecting onedigital signal includes a step of selecting a sequence of digitalsignals from the plurality of first registers at a first data rate; andthe step of transferring the one selected digital signal includes a stepof transferring the sequence of selected digital signals to the secondregister at the first data rate.
 33. The method of claim 32, wherein thestep of respectively storing a plurality of digital signals includessteps of: generating a sequence of digital counts at a second data rate,the second data rate being higher than the first data rate; and storingeach digital signal in the respective first register as one of thesequence of digital counts.
 34. The method of claim 33, wherein the stepof generating includes a step of generating the sequence of digitalcounts as a Gray code to provide each digital signal as a Gray codeddigital signal.
 35. The method of claim 34, wherein after the step oftransferring, the method further includes a step of converting eachselected digital signal transferred to the second register from a Graycoded digital signal to a metastability resolved standard binary digitalsignal.
 36. The method of claim 34, wherein the step of selecting asequence of digital signals includes a step of selecting a sequence ofdigital signals based on an input clock having a first frequency suchthat the sequence of digital signals is selected at the first data rate.37. The method of claim 36, wherein the step of generating includes astep of generating the sequence of digital counts as the Gray code basedon a high speed clock having a second frequency higher than the firstfrequency of the input clock, such that the sequence of digital countsis generated at the second data rate.
 38. The method of claim 37,wherein: each digital signal of the plurality of digital signalsincludes N bits; the Gray code includes a least significant bit; and thestep of generating the sequence of digital counts as the Gray code basedon the high speed clock includes a step of toggling the leastsignificant bit at the second frequency of the high speed clock.
 39. Themethod of claim 38, wherein the step of generating the sequence ofdigital counts as the Gray code based on the high speed clock includes astep of generating at least one of the N bits of the Gray code based onphase shifting of the high speed clock.
 40. The method of claim 39,wherein the step of generating at least one of the N bits of the Graycode based on phase shifting of the high speed clock includes a step ofgenerating the least significant bit as a 90° phase shifted version ofthe high speed clock.